Low Power Design Methodology and Optimization Engineer

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $163,000-$237,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Develop and implement advanced low power design methodologies for CPU architectures.
• Perform detailed power analysis, estimation, and optimization across various design stages.
• Collaborate with RTL design, verification, and physical design teams to integrate power-saving features.
• Drive the adoption of innovative power reduction techniques and tools.
• Contribute to the definition and validation of power management specifications.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience in CPU low power design and optimization.
• Experience with power analysis tools, power intent formats (UPF/CPF), and power reduction techniques.
• Experience with RTL design, synthesis, and static timing analysis.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture, or a related field.
• Experience with power modeling, validation, and post-silicon power debug.
• Proficiency in scripting languages (e.g., Python, Perl) for design automation.