Sr. Engineer, SoC Design Verification

Tenstorrent is seeking an engineer who will focus on pre-silicon verification of DFD logic in advanced AI SoCs, driving coverage of debug, test, and bring-up features critical to silicon success.

This role is hybrid, based out of Boston, MA; Toronto, Ottawa; or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

 

Who You Are

• Deeply curious about silicon debug/test infrastructure and its verification.
• Expert in UVM and verification of DFT/DFD features, scan, and on-chip trace logic.
• Comfortable working with Siemens Tessent flows, iJTAG, and advanced verification automation.
• Proactive, detail-oriented, and thrives in cross-functional technical discussions.
• Ideally familiar with tools similar to CocoTB

 

What We Need

• Develop and own verification environments for DFD logic across AI chiplets and SoCs.
• Write, refine, and execute test scenarios for scan, MBIST, array dump, and clock-stop features.
• Analyze coverage gaps, debug failures, and collaborate closely with DFT and RTL teams.
• Automate flows for JTAG/scanchain testing and integrate AI productivity tools.

 

What You Will Learn

• In-depth DFD/DFT verification using cutting-edge Tessent workflows and scripting.
• Integration of pre-silicon DFD verification with silicon debug strategies.
• How AI-driven automation reshapes modern DV workflows.
• Exposure to security-conscious debug methodologies in advanced SoC designs.

 

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.