Senior Post-Silicon Power & Performance Attainment Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  

THE ROLE

As a member of the Radeon Technologies Group, you will play a critical role in delivering next-generation graphics and compute products from concept to silicon. Working within the Front-End Design and Integration team, you will drive Design-for-Test (DFT) architecture, implementation, and validation for complex SoC designs. You will collaborate closely with Architecture, RTL Design, Physical Design, Verification, and Product Engineering teams to ensure high test coverage, efficient manufacturing test solutions, and successful first-pass silicon bring-up.

This role offers the opportunity to influence DFT strategy across advanced semiconductor products while solving challenging problems at the intersection of design, test, and manufacturing.

THE PERSON

The ideal candidate is a highly motivated engineer with a strong foundation in DFT methodologies and digital design. You possess a deep understanding of scan-based test architectures, ATPG flows, and silicon debug, along with the ability to work effectively across multidisciplinary teams. You are detail-oriented, analytical, and passionate about improving product quality, test efficiency, and manufacturing yield.

KEY RESPONSIBILITIES

• Define, implement, and validate DFT architectures for complex ASIC and SoC designs.
• Develop and integrate DFT features including scan compression, boundary scan, JTAG, and memory BIST solutions.
• Perform scan insertion, DFT synthesis, and ATPG pattern generation to achieve manufacturing test goals.
• Verify ATPG patterns through gate-level simulation and debug test-related issues throughout the design cycle.
• Analyze test coverage, fault models, and manufacturing test effectiveness, driving improvements in quality and test cost.
• Collaborate with Physical Design teams to ensure successful DFT implementation and timing closure.
• Support silicon bring-up, production ramp, and yield learning activities by analyzing test results and driving root-cause resolution.
• Partner with design, verification, and product engineering teams to develop scalable DFT methodologies and best practices.
• Contribute to continuous improvement of DFT flows, automation, and infrastructure.

PREFERRED EXPERIENCE

• Strong understanding of Design-for-Test methodologies, including Scan, Scan Compression, IEEE 1500, IEEE 1149.x (JTAG), Memory BIST, and boundary scan architectures.
• Hands-on experience with industry-standard DFT and ATPG tools such as Synopsys DFTMAX/TetraMAX or Siemens EDA Tessent/TestKompress.
• Experience with gate-level simulation and test pattern validation using tools such as Synopsys VCS.
• Knowledge of digital design flows, synthesis, timing analysis, and physical design considerations.
• Proficiency in Verilog/SystemVerilog and scripting languages such as Perl, Python, Tcl, or Shell.
• Experience debugging silicon and supporting manufacturing test bring-up is highly desirable.
• Familiarity with advanced process-node ASIC or SoC development is a plus.

ACADEMIC CREDENTIALS

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline.

 

This role is not eligible for visa sponsorship.

 

#LI-BW2

#LI-HYBRID

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.

THE ROLE

As a member of the Radeon Technologies Group, you will play a critical role in delivering next-generation graphics and compute products from concept to silicon. Working within the Front-End Design and Integration team, you will drive Design-for-Test (DFT) architecture, implementation, and validation for complex SoC designs. You will collaborate closely with Architecture, RTL Design, Physical Design, Verification, and Product Engineering teams to ensure high test coverage, efficient manufacturing test solutions, and successful first-pass silicon bring-up.

This role offers the opportunity to influence DFT strategy across advanced semiconductor products while solving challenging problems at the intersection of design, test, and manufacturing.

THE PERSON

The ideal candidate is a highly motivated engineer with a strong foundation in DFT methodologies and digital design. You possess a deep understanding of scan-based test architectures, ATPG flows, and silicon debug, along with the ability to work effectively across multidisciplinary teams. You are detail-oriented, analytical, and passionate about improving product quality, test efficiency, and manufacturing yield.

KEY RESPONSIBILITIES

• Define, implement, and validate DFT architectures for complex ASIC and SoC designs.
• Develop and integrate DFT features including scan compression, boundary scan, JTAG, and memory BIST solutions.
• Perform scan insertion, DFT synthesis, and ATPG pattern generation to achieve manufacturing test goals.
• Verify ATPG patterns through gate-level simulation and debug test-related issues throughout the design cycle.
• Analyze test coverage, fault models, and manufacturing test effectiveness, driving improvements in quality and test cost.
• Collaborate with Physical Design teams to ensure successful DFT implementation and timing closure.
• Support silicon bring-up, production ramp, and yield learning activities by analyzing test results and driving root-cause resolution.
• Partner with design, verification, and product engineering teams to develop scalable DFT methodologies and best practices.
• Contribute to continuous improvement of DFT flows, automation, and infrastructure.

PREFERRED EXPERIENCE

• Strong understanding of Design-for-Test methodologies, including Scan, Scan Compression, IEEE 1500, IEEE 1149.x (JTAG), Memory BIST, and boundary scan architectures.
• Hands-on experience with industry-standard DFT and ATPG tools such as Synopsys DFTMAX/TetraMAX or Siemens EDA Tessent/TestKompress.
• Experience with gate-level simulation and test pattern validation using tools such as Synopsys VCS.
• Knowledge of digital design flows, synthesis, timing analysis, and physical design considerations.
• Proficiency in Verilog/SystemVerilog and scripting languages such as Perl, Python, Tcl, or Shell.
• Experience debugging silicon and supporting manufacturing test bring-up is highly desirable.
• Familiarity with advanced process-node ASIC or SoC development is a plus.

ACADEMIC CREDENTIALS

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline.

 

This role is not eligible for visa sponsorship.

 

#LI-BW2

#LI-HYBRID

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.