at AMD
Location
Santa Clara, California
Compensation
$203k–$348k USD
Type
full time
Posted
Yesterday
Remote
Yes
Market range · company + function + seniority
p25 · target · p75 · n=226
Posted $348k · well above market
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WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
AMD is looking for an engineering leader passionate about driving the best Power, Performance, Area (PPA) of AMD’s SoC coherent Interconnects Data Fabrics IPs for next generation AMD AI devices. The ideal candidate will have proven experience in developing scalable complex digital IP microarchitectures to deliver industry leading performance/area and performance/power. In this role the candidate will work with IP and SOC Architecture team, RTL design team, verification team, and physical design team to drive the RTL design and microarchitecture of modular network on chip IPs for AMD Data Center silicon SoCs. The candidate will drive new methodologies to build scalable, modular network on chips. You will be a member of a core team of incredibly talented industry specialists and will work with the latest and rapidly evolving hardware technologies for AMD Data Center SoCs.
THE PERSON:
The ideal candidate has passion for modern, complex microarchitecture, and efficient digital design. Should have demonstrated experience in developing complex highly scalable, modular microarchitectures for SOC with focus on coherent and non-coherent switch fabric IP and must possess leadership and technical skills to influence and drive SOC methodologies to enable delivery of multiple highly complex, high quality, SoCs in shorter time. Able to communicate effectively and work optimally with different teams across AMD.
KEY RESPONSIBILITIES:
PREFERRED EXPERIENCE:
ACADEMIC CREDENTIALS:
LOCATION: Santa Clara, Ca
This role is not eligible for visa sponsorship.
#LI-MR1
#LI-Hybrid
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
THE ROLE:
AMD is looking for an engineering leader passionate about driving the best Power, Performance, Area (PPA) of AMD’s SoC coherent Interconnects Data Fabrics IPs for next generation AMD AI devices. The ideal candidate will have proven experience in developing scalable complex digital IP microarchitectures to deliver industry leading performance/area and performance/power. In this role the candidate will work with IP and SOC Architecture team, RTL design team, verification team, and physical design team to drive the RTL design and microarchitecture of modular network on chip IPs for AMD Data Center silicon SoCs. The candidate will drive new methodologies to build scalable, modular network on chips. You will be a member of a core team of incredibly talented industry specialists and will work with the latest and rapidly evolving hardware technologies for AMD Data Center SoCs.
THE PERSON:
The ideal candidate has passion for modern, complex microarchitecture, and efficient digital design. Should have demonstrated experience in developing complex highly scalable, modular microarchitectures for SOC with focus on coherent and non-coherent switch fabric IP and must possess leadership and technical skills to influence and drive SOC methodologies to enable delivery of multiple highly complex, high quality, SoCs in shorter time. Able to communicate effectively and work optimally with different teams across AMD.
KEY RESPONSIBILITIES:
PREFERRED EXPERIENCE:
ACADEMIC CREDENTIALS:
LOCATION: Santa Clara, Ca
This role is not eligible for visa sponsorship.
#LI-MR1
#LI-Hybrid
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
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