VLSI RTL design engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  

THE ROLE: 

AMD’s Cores Organization delivers industry leading CPU’s, Caches, and Chiplets that are the foundation of AMD’s server, client, and gaming business.  We are looking for an experienced VLSI RTL design engineer to join this innovative team.  In this role, the candidate will invent and implement the highest performance, most energy efficient cache and fabric designs in the industry. The candidate will have the potential and will develop to be a key contributor and leader for AMD’s next generation cores and caches.  The candidate will join the team based in Fort Collins, CO

 

THE PERSON: 

We are pushing the envelope on chip performance, so the status quo must be challenged on every program. This environment requires creativity and innovation, but also excellent verbal and written communication skills. The candidate has strong analytical thinking and problem-solving skills and enjoys using those skills to accomplish goals that many might not think possible. The candidate is a multiplier and has experience fostering collaboration across a broad spectrum of team boundaries.

 

KEY RESPONSIBILITIES: 

• Collaborate with Cache and CPU Architects to design, document, and execute optimized high-performance Cache and Routing Fabric designs.

• Collaborate with Physical Design to develop RTL that is optimized for physical construction and timing closure.
• Collaborate with Design Verification to develop architecture and features that are documented clearly and are verifiable.
• Collaborate with Design For Test teams to develop RTL that is reliable, testable, and manufacturable.
• Work across global teams to solve complex architectural interactions between IP and SOC designs
• Develop ways to improve our CPU design by increasing quality, by simplifying design complexities through innovation, and by improving our technical interactions with other teams
• Solve design and tool problems requiring ground-breaking approaches and champion innovation across the organization.  Create technical presentations for peers and management.

 

PREFERRED EXPERIENCE: 

• Prior SRAM, Coherent Cache or interconnect/NOC RTL design experience
• Prior experience with Digital RTL Design, Verilog HDL, Software Development, and Scripting

 

ACADEMIC CREDENTIALS: 

• BS/MS in EE, CS, CSE (or similar), plus 3+ years hardware design experience

 

This role is not eligible for visa sponsorship.

 

LOCATION: Ft. Collins, Co; possibly Austin, Tx

 

#LI-MR1

#LI-Hybrid

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.

THE ROLE: 

AMD’s Cores Organization delivers industry leading CPU’s, Caches, and Chiplets that are the foundation of AMD’s server, client, and gaming business.  We are looking for an experienced VLSI RTL design engineer to join this innovative team.  In this role, the candidate will invent and implement the highest performance, most energy efficient cache and fabric designs in the industry. The candidate will have the potential and will develop to be a key contributor and leader for AMD’s next generation cores and caches.  The candidate will join the team based in Fort Collins, CO

 

THE PERSON: 

We are pushing the envelope on chip performance, so the status quo must be challenged on every program. This environment requires creativity and innovation, but also excellent verbal and written communication skills. The candidate has strong analytical thinking and problem-solving skills and enjoys using those skills to accomplish goals that many might not think possible. The candidate is a multiplier and has experience fostering collaboration across a broad spectrum of team boundaries.

 

KEY RESPONSIBILITIES: 

• Collaborate with Cache and CPU Architects to design, document, and execute optimized high-performance Cache and Routing Fabric designs.

• Collaborate with Physical Design to develop RTL that is optimized for physical construction and timing closure.
• Collaborate with Design Verification to develop architecture and features that are documented clearly and are verifiable.
• Collaborate with Design For Test teams to develop RTL that is reliable, testable, and manufacturable.
• Work across global teams to solve complex architectural interactions between IP and SOC designs
• Develop ways to improve our CPU design by increasing quality, by simplifying design complexities through innovation, and by improving our technical interactions with other teams
• Solve design and tool problems requiring ground-breaking approaches and champion innovation across the organization.  Create technical presentations for peers and management.

 

PREFERRED EXPERIENCE: 

• Prior SRAM, Coherent Cache or interconnect/NOC RTL design experience
• Prior experience with Digital RTL Design, Verilog HDL, Software Development, and Scripting

 

ACADEMIC CREDENTIALS: 

• BS/MS in EE, CS, CSE (or similar), plus 3+ years hardware design experience

 

This role is not eligible for visa sponsorship.

 

LOCATION: Ft. Collins, Co; possibly Austin, Tx

 

#LI-MR1

#LI-Hybrid

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.