RTL Power Management Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  

THE ROLE: 

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design.   

  

THE PERSON:  

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

  

KEY RESPONSIBILITIES:  

• Own the design and implementation of blocks to meet functional, timing, area and power requirements 
• Guide and review verification for these blocks
• Design and implement logic functions that enable efficient test and debug
• Implement automation to increase design team efficiency
• Perform vector-based and vector-less power estimation for different use case scenarios and analyze results to identify areas for improvement.
• Drive static and dynamic power analysis and optimization for complex SoCs and IP blocks.
• Drive low-power design strategies.
• Power domain/island creation (with UPF).
• Develop and maintain power analysis flows using industry-standard EDA tools and emerging, cutting-edge methodologies.
• Correlate RTL power estimates with gate-level and post-layout power results.

 

PREFERRED EXPERIENCE:  

• Strong front-end RTL engineering background
• Expertise with low-power design methodologies and trade-offs.
• Hands-on expertise with EDA tools such as PrimeTime, PrimePower, Power Artist.
• Experience designing with multiple power domains and islands using UPF.
• Strong communication skills, able to summarize complex problems for executives as well as drill down to details with architects and engineers
• Strong analytic and problem solving skills including the ability to analyze current behavior, identify potential areas for improvement, and design of experiments
• Experience with Arm architecture and APB, AXI, CHI protocols
• Experience with design reuse, including RTL, constraints, and waivers
• Experience with SoC level design integration
• Experience with automation using scripting techniques such as PERL, Python, or Tcl
• Experience with timing constraints and timing exceptions
• Experience running standard quality checks such as LINT and CDC
• Experience designing with multiple power domains including writing UPF
• Must be a self-starter and self-motivated

  

ACADEMIC CREDENTIALS:  

• Bachelors or Masters degree in computer engineering/Electrical Engineering 

 

This role is not eligible for visa sponsorship.

 

#LI-RW1

#LI-HYBRID

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.

THE ROLE: 

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design.   

  

THE PERSON:  

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

  

KEY RESPONSIBILITIES:  

• Own the design and implementation of blocks to meet functional, timing, area and power requirements 
• Guide and review verification for these blocks
• Design and implement logic functions that enable efficient test and debug
• Implement automation to increase design team efficiency
• Perform vector-based and vector-less power estimation for different use case scenarios and analyze results to identify areas for improvement.
• Drive static and dynamic power analysis and optimization for complex SoCs and IP blocks.
• Drive low-power design strategies.
• Power domain/island creation (with UPF).
• Develop and maintain power analysis flows using industry-standard EDA tools and emerging, cutting-edge methodologies.
• Correlate RTL power estimates with gate-level and post-layout power results.

 

PREFERRED EXPERIENCE:  

• Strong front-end RTL engineering background
• Expertise with low-power design methodologies and trade-offs.
• Hands-on expertise with EDA tools such as PrimeTime, PrimePower, Power Artist.
• Experience designing with multiple power domains and islands using UPF.
• Strong communication skills, able to summarize complex problems for executives as well as drill down to details with architects and engineers
• Strong analytic and problem solving skills including the ability to analyze current behavior, identify potential areas for improvement, and design of experiments
• Experience with Arm architecture and APB, AXI, CHI protocols
• Experience with design reuse, including RTL, constraints, and waivers
• Experience with SoC level design integration
• Experience with automation using scripting techniques such as PERL, Python, or Tcl
• Experience with timing constraints and timing exceptions
• Experience running standard quality checks such as LINT and CDC
• Experience designing with multiple power domains including writing UPF
• Must be a self-starter and self-motivated

  

ACADEMIC CREDENTIALS:  

• Bachelors or Masters degree in computer engineering/Electrical Engineering 

 

This role is not eligible for visa sponsorship.

 

#LI-RW1

#LI-HYBRID

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.