Technical Lead Manager, Machine Learning, Memory Subsystem Design

As Technical Manager for TPU DRAM, you will develop and validate high performance memory subsystems for upcoming machine learning products.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $240,000-$334,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Lead, mentor and manage a team of RTL Design and DV Engineers developing DRAM subsystems including HBM.
• Collaborate closely with the cross-functional teams (e.g. Design for Test, Signal/Power Integrity, Packaging, Physical Design,Software, Silicon Validation, Silicon Engineering) to plan and execute throughout the development cycle.
• Interface with third party IP providers of memory related IP including controllers, physical layers, and verification models during the selection and implementation phases of projects.
• Interface with DRAM manufacturers during the design and validation of DRAM subsystems.
• Drive improvements in design methodologies, processes, and quality control measures.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 15 years of experience in semiconductor design or design verification.
• 6 years of experience in people management, developing employees.
  
• Experience in designing or verifying DRAM-based memory subsystems.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience in creating and validating HBM-based memory subsystems.