Principal Analog Layout Engineer

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Marvell Central Engineering (CE) develops Marvell's most advanced High-Speed SerDes (HSS) IPs covering multiple applications, Switch, Storage, Optics, etc. Acting as the engine to the company, Central Engineering provides the source of power to every business unit in Marvell system. Central System Engineering (CSE) in Central Engineering, independent of other CE functions including DSP algorithm development, circuit design, physical design, packaging, etc., is a function team responsible of validating all Marvell HSS IPs in the lab environment and supporting all Marvell business units for fast and smooth SoC production. Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products.

This is a rare foundational engineering opportunity as part of our strategic expansion into Southern California. You will help shape the technical DNA and culture of Marvell's San Diego design organization.

What You Can Expect

• Drawing layouts for schematics created by Circuit Design Engineers, using industry standard CAD tools, in deep sub-micron, FinFET technologies.

• Effectively communicate with Design Engineers to clarify and realize the layout requirements based on the schematic functions.

• Provide feedback to Circuit Design Engineers on any modifications to schematics after layouts are completed.

• Interact with Physical Verification (PV) team to analyze DRC, LVS, ANT, ERC, and EMIR results and achieve PV closure.

• Adhere to Marvell’s core behaviors and strive to continuously improve your skills as an Analog Layout Engineer.

• Experienced in Cadence “Virtuoso VXL” and/or Synopsys “Custom Compiler” layout tools.

• Experienced in Mentor Graphics “Calibre” drc/lvs verification tool.

• Good problem-solving skills.

• Strong communication and presentation skills.

• Ability to work independently as well as in teams, including remote design teams.

• Ability to work across functions and levels.

What We're Looking For

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience.
• Master’s degree in Computer Science, Electrical Engineering or related fields with 10-12 years of experience.
• PhD in Computer Science, Electrical Engineering or related fields with 8-10 years of experience.

Expected Base Pay Range (USD)

152,300 - 225,440, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements 

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity 

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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