STA/Constraints Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  

THE ROLE: 

The STA/Constraints Engineer is responsible for developing FullChip constraints and timing closure. Person will work closely with Fellows, Principal Engineers, Architects, collaborate with cross functional worldwide teams across Physical Design, Timing Analysis, Synthesis, Physical Verification, Power signoff, and mentor/coach/guide Design Engineers.

 

KEY RESPONSIBILITIES:  

 

• Own end-to-end delivery of designs (SOC and Sub-system integration) from timing constraints and timing signoff perspective.
• Work closely with the SOC Architecture team for SOC clocks & STA for statistical timing target goals.
• Understanding clock design requirements and making sure they are correctly set up in SDC.
• Understand timing margins (LVF/SSTA/Variations etc.) on the latest tech nodes and work with timing methodology teams for future and current projects.
• Understand design requirements, timelines and various milestones of a project and deliver FCT closure accordingly.
• Collaborate with CAD and EDA vendors to further strengthen AMD timing closure and constraints methodology.
• Responsible for cdc/lint, timing closure, lower power implementation and netlist quality check with RTL designer and PD team.
• Work on SDC development, STA (Static Timing)  analysis, shift left of timing closure, CDC (Clock Domain Crossing).

PREFERRED EXPERIENCE:  

• Industry experience in STA, constraints, timing signoff and physical design
• Expert user of industry-standard PD tools like SNPS PT/GCA (must) and ICC2/FC (desired).
• Good experience and understanding of DFT timing concepts, MBIST, Top level clock -implementation, Place and Route flows -floorplanning and placement, CTS and Route. 
• Good experience with Perl/TCL/Shell/Python scripting, and Verilog RTL design.
• Excellent presentation and inter-communication skills.
• Experience with Verilog RTL design/implementation and has experience of large digital ASIC project.
• Experience with physical design is a plus.
• Has Synthesis or physical implement experience.
• Experience with lower power design methodology.
• Good English skills on talking, presentation and writing documents.
• Good communication and strong sense of responsibility, task scheduling, and time management.

ACADEMIC CREDENTIALS:  

• Bachelor/Master’s degree in Micro Electronics/ Integrated Circuit Science, or related field preferred.

LOCATION: Santa Clara, CA 

 

#LI-HYBRID

#LI-PA1

 

This role is not eligible for visa sponsorship.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.

THE ROLE: 

The STA/Constraints Engineer is responsible for developing FullChip constraints and timing closure. Person will work closely with Fellows, Principal Engineers, Architects, collaborate with cross functional worldwide teams across Physical Design, Timing Analysis, Synthesis, Physical Verification, Power signoff, and mentor/coach/guide Design Engineers.

 

KEY RESPONSIBILITIES:  

 

• Own end-to-end delivery of designs (SOC and Sub-system integration) from timing constraints and timing signoff perspective.
• Work closely with the SOC Architecture team for SOC clocks & STA for statistical timing target goals.
• Understanding clock design requirements and making sure they are correctly set up in SDC.
• Understand timing margins (LVF/SSTA/Variations etc.) on the latest tech nodes and work with timing methodology teams for future and current projects.
• Understand design requirements, timelines and various milestones of a project and deliver FCT closure accordingly.
• Collaborate with CAD and EDA vendors to further strengthen AMD timing closure and constraints methodology.
• Responsible for cdc/lint, timing closure, lower power implementation and netlist quality check with RTL designer and PD team.
• Work on SDC development, STA (Static Timing)  analysis, shift left of timing closure, CDC (Clock Domain Crossing).

PREFERRED EXPERIENCE:  

• Industry experience in STA, constraints, timing signoff and physical design
• Expert user of industry-standard PD tools like SNPS PT/GCA (must) and ICC2/FC (desired).
• Good experience and understanding of DFT timing concepts, MBIST, Top level clock -implementation, Place and Route flows -floorplanning and placement, CTS and Route. 
• Good experience with Perl/TCL/Shell/Python scripting, and Verilog RTL design.
• Excellent presentation and inter-communication skills.
• Experience with Verilog RTL design/implementation and has experience of large digital ASIC project.
• Experience with physical design is a plus.
• Has Synthesis or physical implement experience.
• Experience with lower power design methodology.
• Good English skills on talking, presentation and writing documents.
• Good communication and strong sense of responsibility, task scheduling, and time management.

ACADEMIC CREDENTIALS:  

• Bachelor/Master’s degree in Micro Electronics/ Integrated Circuit Science, or related field preferred.

LOCATION: Santa Clara, CA 

 

#LI-HYBRID

#LI-PA1

 

This role is not eligible for visa sponsorship.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.