at AMD
Location
Boxborough, Massachusetts
Compensation
$156k–$268k USD
Type
full time
Posted
6 days ago
Remote
Yes
Market range · company + function + seniority
p25 · target · p75 · n=112
Posted $268k · in the market band
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WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
The candidate will be a Member of the Memory I/O design team supporting the definition, specification, system simulation and implementation of future LPDDR IPs. The focus of the activity will be centered around the circuit architecture and design of critical high-speed analog and digital blocks, definition of algorithms for calibration, equalization and development of abstracted models for link performance simulations.
THE PERSON:
Will have strong experience building Memory Phys and High-speed IOs with track record of multiple successful Tape-out and productization. The candidate will have analytical thinking and inventive spirit in combination with a solid understanding of risks and risk mitigation. Must have strong/effective communication skills and have an enthusiastic team-first mentality
KEY RESPONSIBILITIES:
Contribute to the definition of circuit architecture and to the design implementation of various state-of-the-art, low power blocks, and area efficient circuits for LPDDR PHY
Design circuits for High Speed IOs that include Transmitter, Receiver – CTLE/DFE, Delay Lines, DAC, OpAmp, Comparator and voltage regulators
Work closely with other teams to port design to different nodes while improving the overall PPA from previous generation
Develop models for link-level statistical performance simulation of the PHY (Link Training, PHY, DRAM, DB/RCD, DFE training, Transmit Equalization) and application of the same to the development and optimization of design.
Documentation of the micro-architecture and algorithms, and guidance of Analog, Digital, Firmware and Verification teams on the training and verification of the circuits.
Work closely with various disciplines, especially Analog Mixed Signal design, Digital Design and Firmware, as well as Design Verification to ensure optimal implementation of the overall PHY architecture and algorithms and full coverage of the features
Participate and contribute to the definition of development flows that improve efficiency and quality of execution
Lead design liaison for post Silicon characterization and productization/volume production efforts
PREFERRED EXPERIENCE:
A proven successful track record in circuit-architecture and modeling for High Speed Ios
A proven track record of leading junior engineers to deliver complex circuits
Solid and hands-on knowledge of algorithms and equalization/calibration/clocking techniques for high-speed circuit design.
Solid knowledge of industry-standard tools and best-in-class practices for PHY modeling, both in terms of abstracted models (e.g. Matlab/Simulink) as well as Verilog/AMS-based.
Good knowledge of IO and system integration (signaling/equalization techniques, signal integrity, power integrity).
Ability to dig into RTL or FW code supporting the custom circuit implementation
ACADEMIC CREDENTIALS:
LOCATION: Boxborough, MA ( open to other AMD locations )
This role is not eligible for visa sponsorship.
#LI-SL3
#LI-HYBRID
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
THE ROLE:
The candidate will be a Member of the Memory I/O design team supporting the definition, specification, system simulation and implementation of future LPDDR IPs. The focus of the activity will be centered around the circuit architecture and design of critical high-speed analog and digital blocks, definition of algorithms for calibration, equalization and development of abstracted models for link performance simulations.
THE PERSON:
Will have strong experience building Memory Phys and High-speed IOs with track record of multiple successful Tape-out and productization. The candidate will have analytical thinking and inventive spirit in combination with a solid understanding of risks and risk mitigation. Must have strong/effective communication skills and have an enthusiastic team-first mentality
KEY RESPONSIBILITIES:
Contribute to the definition of circuit architecture and to the design implementation of various state-of-the-art, low power blocks, and area efficient circuits for LPDDR PHY
Design circuits for High Speed IOs that include Transmitter, Receiver – CTLE/DFE, Delay Lines, DAC, OpAmp, Comparator and voltage regulators
Work closely with other teams to port design to different nodes while improving the overall PPA from previous generation
Develop models for link-level statistical performance simulation of the PHY (Link Training, PHY, DRAM, DB/RCD, DFE training, Transmit Equalization) and application of the same to the development and optimization of design.
Documentation of the micro-architecture and algorithms, and guidance of Analog, Digital, Firmware and Verification teams on the training and verification of the circuits.
Work closely with various disciplines, especially Analog Mixed Signal design, Digital Design and Firmware, as well as Design Verification to ensure optimal implementation of the overall PHY architecture and algorithms and full coverage of the features
Participate and contribute to the definition of development flows that improve efficiency and quality of execution
Lead design liaison for post Silicon characterization and productization/volume production efforts
PREFERRED EXPERIENCE:
A proven successful track record in circuit-architecture and modeling for High Speed Ios
A proven track record of leading junior engineers to deliver complex circuits
Solid and hands-on knowledge of algorithms and equalization/calibration/clocking techniques for high-speed circuit design.
Solid knowledge of industry-standard tools and best-in-class practices for PHY modeling, both in terms of abstracted models (e.g. Matlab/Simulink) as well as Verilog/AMS-based.
Good knowledge of IO and system integration (signaling/equalization techniques, signal integrity, power integrity).
Ability to dig into RTL or FW code supporting the custom circuit implementation
ACADEMIC CREDENTIALS:
LOCATION: Boxborough, MA ( open to other AMD locations )
This role is not eligible for visa sponsorship.
#LI-SL3
#LI-HYBRID
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
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