DFx Methodology Architect

WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  

THE ROLE: 

AECG organization at AMD is looking for an experienced DFx Architecture, Methodology and Logic Design Expert with strengths in RTL and Timing to support FPGA-SoCs and custom ASICs. In this role, you will own and drive DFx Architecture definition, RTL implementation and methodology development.

    

THE PERSON:  

You have had significant success driving Architecture, Design Methodologies, RTL, and Timing to tape out and production. You are meticulous about Power, Performance and Area while driving schedule and managing cost. This role will stretch you as you lead design teams in new directions, network with our world-class, patent-holding think-tank, and negotiate amongst design, verification, validation, CAD and product engineering teams. You have excellent communication, presentation and problem-solving skills. The candidate should be comfortable working hands-on. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.

  

KEY RESPONSIBILITIES:  

• Define and lead SoC-DFx Architecture, Specifications and development of DFx-IPs
• Own DFx Architecture documentation, accounting for interactions with other features, the hardware and the firmware
• Implement DFx features in RTL using Verilog/SystemVerilog
• Co-owning Timing and Design Quality Checks (and waivers) for the DFx-IPs

• Work cross functionally with DFx execution and verification teams to enable integration and validation of DFx-IPs in all phases of design implementation flow
• Work closely with Design teams for Verification Test plan reviews, Timing targets and Performance/Power Verification sign offs
• Engage with validation and product teams on test plan, coverage, Silicon bring up and silicon debug
• Contribute to front-end, DFx and timing methodologies
• Drive innovation in a rapidly changing technological environment

  

PREFERRED EXPERIENCE:  

• Proficient with Siemens Tessent DFT flows, such as Tessent Shell, Tessent Scan, Tessent ATPG, Tessent MemoryBist, IJTAG and SSN
• Understanding of 1149.1 / 1687 standards, understanding of ATPG, experience in 2.5D and 3D IC testing
• Strong understanding of DFT Architecture and Debug methodologies
• Strong foundation in logic design, switching theory and timing
• Experience with supporting silicon debug and diagnosis
• Skilled at collaborating with teams across different geographies

• Scripting language experience: Perl, Python and TCL 

• Exposure to leadership or mentorship is an asset   

  

ACADEMIC CREDENTIALS:  

• Bachelors or Masters or PhD degree in computer engineering/Electrical Engineering 

 

This role is not eligible for visa sponsorship.

 

#LI-CJ3

#LI-Hybrid

 

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.

THE ROLE: 

AECG organization at AMD is looking for an experienced DFx Architecture, Methodology and Logic Design Expert with strengths in RTL and Timing to support FPGA-SoCs and custom ASICs. In this role, you will own and drive DFx Architecture definition, RTL implementation and methodology development.

    

THE PERSON:  

You have had significant success driving Architecture, Design Methodologies, RTL, and Timing to tape out and production. You are meticulous about Power, Performance and Area while driving schedule and managing cost. This role will stretch you as you lead design teams in new directions, network with our world-class, patent-holding think-tank, and negotiate amongst design, verification, validation, CAD and product engineering teams. You have excellent communication, presentation and problem-solving skills. The candidate should be comfortable working hands-on. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.

  

KEY RESPONSIBILITIES:  

• Define and lead SoC-DFx Architecture, Specifications and development of DFx-IPs
• Own DFx Architecture documentation, accounting for interactions with other features, the hardware and the firmware
• Implement DFx features in RTL using Verilog/SystemVerilog
• Co-owning Timing and Design Quality Checks (and waivers) for the DFx-IPs

• Work cross functionally with DFx execution and verification teams to enable integration and validation of DFx-IPs in all phases of design implementation flow
• Work closely with Design teams for Verification Test plan reviews, Timing targets and Performance/Power Verification sign offs
• Engage with validation and product teams on test plan, coverage, Silicon bring up and silicon debug
• Contribute to front-end, DFx and timing methodologies
• Drive innovation in a rapidly changing technological environment

  

PREFERRED EXPERIENCE:  

• Proficient with Siemens Tessent DFT flows, such as Tessent Shell, Tessent Scan, Tessent ATPG, Tessent MemoryBist, IJTAG and SSN
• Understanding of 1149.1 / 1687 standards, understanding of ATPG, experience in 2.5D and 3D IC testing
• Strong understanding of DFT Architecture and Debug methodologies
• Strong foundation in logic design, switching theory and timing
• Experience with supporting silicon debug and diagnosis
• Skilled at collaborating with teams across different geographies

• Scripting language experience: Perl, Python and TCL 

• Exposure to leadership or mentorship is an asset   

  

ACADEMIC CREDENTIALS:  

• Bachelors or Masters or PhD degree in computer engineering/Electrical Engineering 

 

This role is not eligible for visa sponsorship.

 

#LI-CJ3

#LI-Hybrid

 

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.