Staff Engineer, SRAM Layout

What You’ll Do

We are looking for a passionate and experienced Staff Engineer, SRAM Layout to lead the development of next-generation SRAM solutions.

• Lead the development and execution of full-custom SRAM memory layout and sign-off verification flows (including compiler automation where applicable).
• Collaborate closely with circuit designers to translate schematics into efficient, high-performance physical layouts, own floor planning, placement, routing, and tape-out.
• Design and optimize SRAM layouts at the cell, array, and peripheral levels for area, speed, power, yield, and manufacturability.
• Perform and close all physical verification; DRC, LVS, ERC, antenna checks, custom memory rules, RC extraction, parasitic analysis, and signal integrity verification.
• Debug and resolve layout issues efficiently, including process-specific challenges in advanced nodes.
• Lead layout reviews, mentor junior engineers, and drive best practices, optimization techniques, design-rule compliance, and knowledge sharing.
• Develop automation scripts (Perl, Tcl, SKILL, etc.) to improve productivity.
• Address reliability concerns such as EM/IR drop, soft errors, and process variability. 
• Work cross-functionally with circuit, architecture, verification, and foundry/process teams to ensure first-pass silicon success and support product integration

What You Bring

• Bachelor's degree with 10+ years of experience in custom SRAM, memory compiler and IC physical layout design or master's degree 8+ years of experience strongly preferred. 
• 3 year’s experience in leadership of management role preferred.
• Extensive experience in SRAM layout design in advanced process nodes (e.g., 3nm, 2nm, or below).
• Demonstrated ability to lead, mentor, and manage a team of layout engineers. 
• Strong project management skills to handle complex schedules and cross-functional collaboration. 
• Strong proficiency with industry-standard EDA tools: 
• Candence Virtuoso (or Custom Compiler/IC Compiler) for custom/analog layout. 
• Physical verification tools for DRC/LVS/ERC flows. 
• Perform and close all physical verification; DRC, LVS, ERC, antenna checks, custom memory rules, RC extraction, parasitic analysis, and signal integrity verification. 
• Experience with RC extraction, parasitic reduction, and memory-specific verification. 
• Scripting/automation skills (Perl, Tcl, SKILL, etc.) are highly valued. 
• Proven ability to drive layout quality, constraints, and closure while collaborating in global, cross -functional teams. 
• Prior work on high-speed, low-power SRAM in leading-edge nodes preferred. 
• Mentoring or technical leadership experience preferred. 
• Understanding of SRAM architecture, timing, power analysis, and yield optimization preferred. 
• You’re inclusive, adapting your style to the situation and diverse global norms of our people. 
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. 
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. 
• Innovative and creative, you proactively explore new ideas and adapt quickly to change

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