Meta's Infrastructure Silicon team is seeking a Staff ASIC Design Verification Engineer to lead verification strategy and execution for custom silicon powering Meta's data center infrastructure. In this role, you will architect and drive end-to-end verification of complex IP blocks and SoCs designed for AI/ML acceleration, networking, and storage workloads. You will define scalable UVM-based verification environments, establish coverage closure methodologies, and partner with design, emulation, and post-silicon validation teams to ensure first-pass silicon success across Meta's infrastructure ASIC portfolio.
Responsibilities
- Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
- Develop functional tests based on the verification test plan
- Drive design verification to closure based on defined verification metrics on the test plan, functional, and code coverage
- Debug, root-cause and resolve functional failures in the design, partnering with the design team
- Collaborate with cross-functional teams like Design, Model, Emulation, and silicon validation teams towards ensuring the highest design quality
- Develop and drive continuous design verification improvements using the latest verification methodologies, tools, and technologies from the industry
Minimum Qualifications
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
- Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience
- 8+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification
- 8+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
- Experience in one or more of the following areas, along with functional verification, SV assertions, formal, and emulation
- Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
- Experience in architecting and implementing design verification infrastructure and executing the full verification cycle
- Familiarity with power management verification concepts Experience verifying compute, memory, or interconnect subsystems within AI/ML accelerator or data center networking SoCs
- Experience with ARM, RISC-V, or GPU-based subsystem verification at the IP or full-chip level
- Familiarity with host and system-level software stacks as they relate to hardware functional verification and stimulus generation
- Experience with chiplet-based architectures and package-level integration verification methodologies