CPU Global Design Lead, Silicon

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $240000 - $334000 (USD) + 25% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

• Participate in developing CPU subsystem. Develop CPU subsystem front-end designs, emphasizing microarchitecture and RTL design for the next generation CPU.
• Propose performance enhancing microarchitecture features, and work with Software, Architect, and Performance teams for trade-off studies.
• Communicate the pros and cons of microarchitecture enhancements. Deliver designs, meeting PPA goals with production quality.
• Work with the Verification team to ensure production of quality designs, and the physical design and power teams to meet frequency, power, and area goals.
• Become familiar with modern techniques, interpret the techniques into design constructs, and languages in order to provide guidance to and participate in the performance evaluation effort.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 15 years of experience in CPU or AI accelerator logic/RTL design, including microarchitecture definition and Power, Performance, and Area (PPA) optimizations.
• Experience with RTL language (System Verilog) and related design processes (e.g., Lint, UPF).

Preferred qualifications:

• PhD in Electrical Engineering or Computer Science.
• Experience leading front-end design for modern processor components or AI accelerators.
• Experience with ARM Instruction Set Architecture.
• Experience with SOC design, architect, and integration.