ASIC Design Verification Engineer, Google Cloud

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As an Application-Specific Integrated Circuit (ASIC) Design Verification Engineer, you will be part of a team developing ASICs used to accelerate computation in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design verification, and silicon bringup. You will participate in the architecture, documentation, and verification of the next generation of data center accelerators.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Plan the verification of complex digital design blocks, understand the design specification, and interact with design engineers to identify important verification scenarios.
• Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM).
• Identify and write all types of coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to deliver correct design blocks.
• Close coverage measures to identify verification holes and to show progress towards tape-out.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  
• 1 year of experience in design verification.
• Experience with SystemVerilog/Verilog.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with Universal Verification Methodology (UVM) testbenches and methodologies.
• Experience developing and executing test plans.
• Familiarity with coverage analysis tools (e.g., Verdi, Questa).
• Proficiency in SystemVerilog, including object-oriented programming, SystemVerilog Assertions (SVAs) and functional coverage.
• Excellent problem-solving and debugging skills.