Principal ASIC Design Engineer - PCIe / High-Speed I/O

WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  

THE ROLE: 

You will contribute to the ASIC (chip) design for high-performance network chips: AINIC and DPU. As a member of the NTSG ASIC Design Team, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.
THE PERSON:

A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

KEY RESPONSIBLITIES:

• PCIe architecture, design, and integration
• Front-end RTL design and integration of high-speed I/O subsystems
• Collaboration with architecture, IP, and physical design teams for first-pass silicon success
• Post-silicon bring-up support and yield learning

PREFERRED EXPERIENCE:

• Deep understanding of PCIe Transaction layer, Data Link layer, and Physical layer protocols and behaviors
• Understanding of high-speed I/O (SerDes) architecture, design, and verification
• Experience with VCS simulation tool, Perl/Python/Shell scripting, and SystemVerilog/Verilog RTL design

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering 

LOCATION:

Santa Clara, CA

 

This role is not eligible for visa sponsorship.

 

#LI-BW1

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.

THE ROLE: 

You will contribute to the ASIC (chip) design for high-performance network chips: AINIC and DPU. As a member of the NTSG ASIC Design Team, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.
THE PERSON:

A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

KEY RESPONSIBLITIES:

• PCIe architecture, design, and integration
• Front-end RTL design and integration of high-speed I/O subsystems
• Collaboration with architecture, IP, and physical design teams for first-pass silicon success
• Post-silicon bring-up support and yield learning

PREFERRED EXPERIENCE:

• Deep understanding of PCIe Transaction layer, Data Link layer, and Physical layer protocols and behaviors
• Understanding of high-speed I/O (SerDes) architecture, design, and verification
• Experience with VCS simulation tool, Perl/Python/Shell scripting, and SystemVerilog/Verilog RTL design

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering 

LOCATION:

Santa Clara, CA

 

This role is not eligible for visa sponsorship.

 

#LI-BW1

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.