PCB Layout Engineer

Tenstorrent is seeking a Layout Engineer with expertise in board layout for high-performance computing and  AI hardware. This role requires direct experience with multi-layer boards, HDI vias, blind vias, back drilling, DFM, DFA and routing / layout of interfaces like GDDR, LPDDR, DDR, PCIe Gen 5 & 6, Ethernet IEEE 802.3bj, cd, cf, USB, etc. The ideal candidate will work closely with cross-functional teams consisting of engineers from systems, power, signal integrity and mechanical to ensure that our products meet the layout margins and cutting-edge specifications for mass production boards for data centers, workstations, and consumer computing applications.

This role is hybrid, based out of Toronto, ON or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

 

Who you are

• Experienced board layout engineer with ~8+ years in PCB design (Cadence Allegro; Altium a plus).
• Hold a B.S. in EE, CS, or equivalent experience.
• Strong background in high-speed, complex PCBs (high layer count, HDI, multi-lamination, VIPPO, back drilling).
• Comfortable defining and applying layout rules (physical, spacing, length-matching) for high-speed designs.
• Confident working with fabricators on stackups, capabilities, and resolving DFM/DFA/DFT feedback.
• Detail-oriented owner of designs with strong communication skills and the ability to work with an international, cross-functional team.

 

What we need

• A Layout Engineer to own multi-layer PCB layouts for high-performance computing and AI hardware.
• Expertise routing GDDR, LPDDR, DDR, PCIe Gen 5/6, Ethernet (IEEE 802.3bj/cd/cf), USB and other high-speed interfaces.
• Proficiency with Cadence schematic/layout tools (v25.1) in the Cadence Pulse environment.
• Ability to choose appropriate advanced fabrication technologies (HDI, blind/buried vias, VIPPO, back drilling) balancing performance and cost.
• Skill in floorplanning, component placement, board connectivity, and creation of power/ground planes.
• Collaboration with power, signal integrity, and mechanical engineers to meet PDN, SI, mechanical, thermal, and regulatory (IPC, UL, CE, RoHS, FCC) requirements.

 

What you will learn

• How to design boards for cutting-edge AI and high-performance computing systems in data center, workstation, and consumer products.
• Techniques to optimize signal integrity, power delivery, and manufacturability for mass-production hardware.
• Best practices for working in a deeply cross-functional environment across systems, power, SI, and mechanical teams.
• Practical experience building around a from-scratch, high-performance RISC-V CPU and AI-first compute platform.
• How to navigate and integrate global industry and regulatory standards while pushing performance limits.
• The direct impact of your layout work on the roadmap and success of a fast-growing AI silicon and systems company.

 

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.