Silicon Architect, AI Power and Performance

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

This role offers the opportunity to work on cutting-edge power management technologies for AI/ML workloads that directly impact the battery life and efficiency of Google's flagship Android devices and custom silicon.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $192,000-$278,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Lead the analysis and implementation of architectural optimizations that span the full stack - from low-level silicon IP to high-level Android frameworks - to maximize AI performance per watt.
• Influence hardware and software roadmaps for SOC, AI accelerators, and emerging memory technologies to meet future Gemini and GenAI product requirements.
• Propose and drive the development of proof-of-concept prototypes for next-generation power management frameworks and specialized AI solutions.
• Act as a primary technical bridge between silicon process, IP design, Android OS, and Gemini model teams to ensure vertical integration and alignment on performance targets.

Minimum qualifications:

• Bachelor’s degree in Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.
• 10 years of experience in silicon architecture, hardware/software co-design, or power and performance modeling.
• Experience in memory architecture, interface, and controller.

Preferred qualifications:

• Master’s degree or PhD with a research focus on computer architecture, next-generation memory systems, or AI hardware accelerators.
• Experience in optimizing hardware and software architectures for Mixture of Experts (MoE) models.
• In-depth understanding of end-to-end data flows for large-scale AI/ML workloads, including prefill, decode, and multimodal processing in LLMs.
• Proven track record of leading new innovation technical workstreams and influencing product roadmaps across multiple organizational boundaries.