Hardware & Silicon Validation Director

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Marvell's Central System Engineering (CSE) group is part of Central Engineering (CE), the engine that powers every Business Unit at Marvell. CSE is an independent function within CE responsible for validating all Marvell High-Speed PHY(Serdes/D2D) IPs, in the lab environment and supporting all Marvell Business Units for fast and smooth SoC production. The team develops data communication system hardware infrastructure and large-scale automation to deliver the highest quality PHY IP and analog macros across Marvell's product portfolio, spanning Switch, Automotive, Storage, Optics, and more.

We are seeking a highly motivated and experienced Validation Director to lead the silicon validation team for our High Speed PHY products. This is a critical leadership role responsible for driving validation strategy, execution, and team development across multiple generations of cutting-edge PHY products operating at 100G+ per lane.

What You Can Expect

• Lead and manage a multi-disciplinary team of silicon validation engineers responsible for post-silicon bring-up, characterization, and compliance testing of high-speed PHY products (Ethernet, PCIe, SerDes).

• Define and own the overall validation strategy, methodology, and test plans for High Speed PHY products from A0 silicon through production release.

• Drive bring-up, debug, and characterization of analog front-end (AFE), ADC/DAC, PLL/DLL, CDR, and SerDes IP blocks at block and system levels.

• Oversee compliance and interoperability testing against industry standards including IEEE 802.3, PCIe Gen 5/6, and other relevant specifications.

• Partner closely with analog/digital design, DSP, firmware, system engineering, and application engineering teams to resolve silicon issues and drive product quality.

• Develop and implement lab automation infrastructure and test frameworks to enable large-scale, high-throughput characterization across PVT corners.

• Own resource planning, headcount management, and budget for the validation organization; work with senior leadership to prioritize programs and allocate resources effectively.

• Establish and maintain strong cross-functional relationships with Business Unit leaders, marketing, and program management to align validation milestones with product schedules.

• Provide technical mentorship and career development guidance to team members; build a high-performing, inclusive team culture.

• Engage with key customers and field application engineers to support customer bring-up, debug, and issue resolution.

• Contribute to the definition of next-generation PHY products by providing validation insights and feedback to design and architecture teams.

What We're Looking For

Basic Qualifications

• BS/MS degree in Electrical Engineering or related technical field.

• 15+ years of experience in semiconductor silicon validation, hardware design, or related disciplines.

• 5+ years of people management experience, with a demonstrated track record of building and leading high-performing engineering teams.

• Deep technical expertise in high-speed PHY validation, including SerDes, Ethernet transceivers (10G–800G), and/or PCIe.

• Hands-on experience with post-silicon bring-up, debug, and characterization of complex mixed-signal ICs.

• Strong working knowledge of lab instrumentation including high-speed oscilloscopes, BERTs, spectrum analyzers, signal generators, and network analyzers.

• Proficiency in scripting and test automation (Python, MATLAB, or equivalent).

• Excellent verbal and written communication skills; ability to present complex technical topics clearly to executive leadership.

Preferred Qualifications

• MS or PhD in Electrical Engineering with focus on high-speed communications or mixed-signal design.

• Experience with IEEE 802.3 Ethernet compliance testing (100G, 400G, 800G) and/or PCIe Gen 5/6 compliance and interoperability.

• Familiarity with signal integrity analysis, eye diagram characterization, and jitter analysis methodologies.

• Experience managing geographically distributed teams across multiple sites.

• Prior experience in a Director-level role within a semiconductor company.

• Knowledge of DSP algorithms and firmware used in high-speed transceiver products.

Expected Base Pay Range (USD)

185,390 - 277,700, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements 

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity 

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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