Advanced Package Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  

THE ROLE: 

We are looking for an Advanced Package Design Engineer who will be responsible for advanced 2.5D & 3D IC packaging technology evaluation, design enablement/implementation, and product development for FPGA and ASIC products from conception to production.

THE PERSON:

The ideal candidate must be familiar with advanced 2.5D and 3D packaging technologies including design/manufacturing flows, vendor eco-system, yield and reliability qualification and enhancement knobs. A good understanding of CAD flows to support robust 3DIC product and package design is essential. The candidate shall possess effective communication, good interpersonal skills and be able to work seamlessly with design teams, foundry partners, package/assembly vendors and validation teams. Typically, the candidate will hold a degree in engineering or physical science with over 10+ years of relevant experience in the field.

 

KEY RESPONSIBILITIES:

• Responsible for 3DIC & Package technology definitions and system-technology co-optimization (STCO) of FPGA and ASIC products in advanced nodes
• Co-work with design, CAD & PDK teams to accomplish robust 3DIC product and substrate designs
• Explore, evaluate and develop new CAD tools, design and verification flow
• Manage design tech files, documentation and databases to enable successful tape-out
• Coordinate testchip design and tape-out for 2.5D & 3DIC technology validation and reliability assessment prior to production
• Pursue product yield analysis and design enhancement through collaboration with foundry and design teams to meet AEGC product need
• Support packaging and 3DIC technology roadmap exploration

 PREFERRED EXPERIENCE:

• Familiar with 2.5D & 3D packaging technologies, including foundry, OSAT, and OEM packaging solutions, advanced interconnect, and substrate technologies.
• Understand key 2.5D and 3D IC product challenges and solutions including cost, signal/power integrity, thermal management, reliability risks etc.  
• Deep understanding of 2.5D and 3D IC manufacturing and reliability design rule requirements
• Possess hand-on experience of major EDA tools to support 3DIC product and package design, physical verification, signal and power integrity check, reliability and thermal validation etc.
• Exceptional data analysis, problem solving, decision making and communication skills
• Working experience in 2.5D & 3D IC testchip, product design and yield analysis is a plus
• Team management and cross-functional team experience is a plus

 ACADEMIC CREDENTIALS:

• Bachelor degree in engineering or physical science, strongly preferred with advanced degree (MS or PhD)

LOCATION:

San Jose, CA

 

This role is not eligible for visa sponsorship.

 

 

#LI-SL2

#LI-HYBRID

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.

THE ROLE: 

We are looking for an Advanced Package Design Engineer who will be responsible for advanced 2.5D & 3D IC packaging technology evaluation, design enablement/implementation, and product development for FPGA and ASIC products from conception to production.

THE PERSON:

The ideal candidate must be familiar with advanced 2.5D and 3D packaging technologies including design/manufacturing flows, vendor eco-system, yield and reliability qualification and enhancement knobs. A good understanding of CAD flows to support robust 3DIC product and package design is essential. The candidate shall possess effective communication, good interpersonal skills and be able to work seamlessly with design teams, foundry partners, package/assembly vendors and validation teams. Typically, the candidate will hold a degree in engineering or physical science with over 10+ years of relevant experience in the field.

 

KEY RESPONSIBILITIES:

• Responsible for 3DIC & Package technology definitions and system-technology co-optimization (STCO) of FPGA and ASIC products in advanced nodes
• Co-work with design, CAD & PDK teams to accomplish robust 3DIC product and substrate designs
• Explore, evaluate and develop new CAD tools, design and verification flow
• Manage design tech files, documentation and databases to enable successful tape-out
• Coordinate testchip design and tape-out for 2.5D & 3DIC technology validation and reliability assessment prior to production
• Pursue product yield analysis and design enhancement through collaboration with foundry and design teams to meet AEGC product need
• Support packaging and 3DIC technology roadmap exploration

 PREFERRED EXPERIENCE:

• Familiar with 2.5D & 3D packaging technologies, including foundry, OSAT, and OEM packaging solutions, advanced interconnect, and substrate technologies.
• Understand key 2.5D and 3D IC product challenges and solutions including cost, signal/power integrity, thermal management, reliability risks etc.  
• Deep understanding of 2.5D and 3D IC manufacturing and reliability design rule requirements
• Possess hand-on experience of major EDA tools to support 3DIC product and package design, physical verification, signal and power integrity check, reliability and thermal validation etc.
• Exceptional data analysis, problem solving, decision making and communication skills
• Working experience in 2.5D & 3D IC testchip, product design and yield analysis is a plus
• Team management and cross-functional team experience is a plus

 ACADEMIC CREDENTIALS:

• Bachelor degree in engineering or physical science, strongly preferred with advanced degree (MS or PhD)

LOCATION:

San Jose, CA

 

This role is not eligible for visa sponsorship.

 

 

#LI-SL2

#LI-HYBRID

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.