Analog Design Engineer, Google Cloud

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a Analog Design Engineer, you are the silicon strategist, defining the architectural path from high-speed electrical interconnects to Co-Packaged Optics (CPO). You will set the technical direction for Google's silicon in the 1.6Tbps era.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $240,000-$334,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Define the specifications for our next-generation Physics Layers (PHYs).
• Identify potential showstoppers in future process nodes and advanced packaging before major Research and Development (R&D) investments are made.
• Set the proven vehicle rule for how the team uses test vehicles to de-risk high-bandwidth silicon and accelerate innovation.
• Represent Google in standards bodies to ensure the industry roadmap aligns with our hyper-scale requirements.
• Act as a primary technical advisor to engineering leadership, mentoring senior members of the team and managing the long-term technical roadmap.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
• 12 years of experience in Analog/Mixed-Signal design.
• Experience with advanced packaging (2.5D/3D) and mixed-signal performance.

Preferred qualifications:

• Master's or PhD degree in Electrical Engineering, Computer Engineering, or a related technical field.
• Experience shipping industry-first silicon.
• Experience with the design and integration of optical interconnects and Co-Packaged Optics (CPO).
• Expertise in high-speed interconnects, with a strong record of publications, patents, or conference presentations.
• Understanding of system-level trade-offs, from device physics to network architecture in hyperscale data centers.
• Ability to influence and drive technical strategy across large, cross-functional organizations.