Staff Design Engineer, Digital Signal Processing

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will be responsible for turning communication theory into efficient, bit-exact silicon logic. You will take high-level models and transform them into the high-speed Digital Signal Processing (DSP) blocks that sit at the heart of our next-gen architecture.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $192,000-$278,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Design and implement DSP algorithms for high-speed PHYs, focusing on FFE/DFE and timing recovery loops.
• Perform rigorous fixed-point analysis to minimize bit-width (Area/Power) while maintaining the required Signal-to-Noise Ratio (SNR).
• Develop bit-exact C++/SystemC models to verify RTL against architectural intent.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
• 10 years of industry experience in Digital Signal Processing (DSP) design or High-Speed Digital Logic design.
• Experience implementing digital blocks for Communication Systems or PHY (Physical Layer) e.g., filters, interpolators, or timing recovery.
• Experience in MATLAB, Python, or C++.

Preferred qualifications:

• Master's or PhD degree in Electrical Engineering, Computer Engineering, or a related technical field.
• Experience with FinFET process nodes (5nm, 3nm) and Timing Closure at GHz frequencies.
• Experience with UVM verification environments.