Silicon Validation Engineer, HBM, Google Cloud

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role you will work on test design, bring-up, triage, and debug of the TPU High Bandwidth Memory (HBM) subsystem across emulation, test chip, and production silicon platforms. You will work closely with Silicon Validation, HBM technologists, and pre-silicon teams during the development phase of the ASIC life-cycle, ensuring proper features are in place for post-silicon validation and debug. Once silicon is in the lab, you will collect and help interpret data alongside system software and software test infrastructure developers to ensure the HBM subsystem has met the threshold for production release.

You will help develop processes and tests to ensure smooth and reliable performance of HBM projects. You will be direct throughout the project lifecycle, from early pre-silicon planning and test development, through end-of-life characterization and failure debug. By leveraging silicon knowledge you will develop and operate software-based tests for full investigation of HBM operation.

You will work closely with hardware and software teams to successfully validate designs, identify design issues, and gain insight into the requirements for full ASIC test coverage.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Develop detailed silicon test plans, based on design specifications and coordination with a cross-functional silicon team (architecture, design, software, firmware) for Google's Tensor Processing Units (TPUs).
• Implement test plans by developing software tests and flows for system validation and verification, then utilize it all to test hardware, collect data, and characterize the operation of HBMs in both test chips and production silicon. 
• Triage and debug issues found during new product development and find solutions.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 2 years of experience in bringing up ASICs, performing functional and performance validation, or debugging failures.
• Experience scripting in Python or a similar programming language.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, or a related field.
• 2 years of experience with C++/Python software design principles.
• Experience bringing up high-power ASICs and working with memories.
• Experience with reading hardware description languages (SystemVerilog) and chip design flow, and building test automation tools and scripts.
• Passion for unusual computer architectures.